What is pre CTS?

September 10, 2022 Chris Normand

In this article, we present a couple of techniques that can be pretty useful in early, or pre-clock tree synthesis (CTS), stages of physical design to help the designers efficiently utilise the time and minimise the effort.

What is pre CTS and post CTS?

It is quite apt to say that backend cycle also consists of two sub-processes – i) Before clock tree has been implemented, also known as pre-clock tree synthesis (CTS) stages; and ii) After clock tree has been implemented (post-CTS stages).

What are the checks after CTS?

Checks after CTS:

In latency report check is skew is minimum? And insertion delay is balanced or not.

Why We Do CTS before routing?

CTS is the stage where this kind of loading is synthesized into a balanced tree to arrive with a min skew and latency for all sinks (flops). Until you finish logical synthesis of clocks, you are not allowed to route anything.

What are the different checks we do in CTS stage?

CTS Quality Checks

Minimize Insertion Delay.
Skew Balancing.
Duty Cycle.
Pulse Width.
Clock Tree power consumption.
Signal Integrity and Crosstalk.

CTS Quality Checks

Minimize Insertion Delay.
Skew Balancing.
Duty Cycle.
Pulse Width.
Clock Tree power consumption.
Signal Integrity and Crosstalk.

What is sink pin?

Sink pins are the clock endpoints that are used for delay balancing. The tool assign an insertion delay of zero to all sink pins and uses this delay during the delay balancing.

What are clock tree types?

A clock tree can have different structures such as:

Fish bone. H-tree. X-tree. Multi-level clock tree.

What is H clock tree?

H-Tree. In this algorithm Clock routing takes place like the English letter H. It is an easy approach that is based on the equalization of wire length. In H tree-based approach the distance from the clock source points to each of the clock sink points are always the same.

How do you set inter clock uncertainty?

Hold ( -hold )— Allows you to specify a clock uncertainty value for clock hold or removal checks. If the hold check is performed on the same edge, the user defined set_clock_uncertainty -hold is ignored by TimeQuest. You can use- enable_same_physical_edge option to account for this hold uncertainty.

What is a clock mesh?

Clock mesh is a clocking scheme employed by high-performance design teams to achieve low skew and high OCV tolerance. The large impact of OCV derating on conventional clock trees motivates mainstream design groups to also consider clock mesh.

What is CCD in physical design?

A charge-coupled device (CCD) is an integrated circuit containing an array of linked, or coupled, capacitors. Under the control of an external circuit, each capacitor can transfer its electric charge to a neighboring capacitor. CCD sensors are a major technology used in digital imaging.

How do you reduce skewness?

The simplest method to help prevent the short data path problem is to minimize the clock skew by using the low-skew global routing resources for clock signals. Microsemi devices provide various types of global routing resources that significantly reduce skew.

What is latency in physical design?

Latency: It is the amount of time a clock signal takes to propagate from the original clock source to the sequential elements in the design. Source latency: It is the delay from the clock source to the clock definition pin in the design.

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